Strip format of package board and array of the same

ABSTRACT

Disclosed herein is a strip format of a semiconductor package board and an array thereof, in which a dummy area of the strip format of the semiconductor package board is formed into a predetermined shape such that, when several strip formats of semiconductor package boards are arranged on a panel, the number of strip formats of semiconductor package boards arranged on the panel can be increased.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No.10-2006-0033266, filed Apr. 12, 2006, entitled “A PACKAGE STRIP FORMATAND ITS ARRAY”, which is hereby incorporated by reference in itsentirety into this application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to strip formats ofsemiconductor package boards and arrays thereof and, more particularly,to a strip format of a semiconductor package board and an array thereofin which a dummy area of the strip format of the semiconductor packageboard is formed into a predetermined shape such that, when several stripformats of semiconductor package boards are arranged on a panel, thenumber of strip formats of semiconductor package boards arranged on thepanel can be increased.

2. Description of the Related Art

As well known to those skilled in the art, the conventional strip formatof a semiconductor package board has the construction shown in FIG. 1.

The construction of the conventional strip format of the semiconductorpackage board will be explained in detail herein below with reference toFIG. 1. Typically, the strip format 10 of the semiconductor packageboard includes a semiconductor package area 11, which has asemiconductor device mounting part 11 a and an outer layer circuitpattern 11 b, and a dummy area 12, which surrounds the semiconductorpackage area 11.

A plurality of strip formats 10 of semiconductor package boards havingthe above-mentioned constructions is arranged on a panel. Here, eachstrip format 10 of the semiconductor package board has a predeterminedstandard size. The panel also has a predetermined standard size.Therefore, the number of semiconductor package boards that can bemounted to the panel is set at a predetermined value.

The arrangement of strip formats of semiconductor package boards on thepanel is shown in FIG. 2. Referring to FIG. 2, a predetermined number ofstrip formats 10 of semiconductor package boards is arranged on thepanel 20.

That is, in this drawing, ten strip formats 10 of semiconductor packageboards are arranged on the panel 20. As such, it will be appreciatedthat, because the shape of the strip format 10 of each semiconductorpackage board and the shape of the panel 20 are standardized, the numberof strip formats 10 of semiconductor package boards that can be mountedto the panel 20 is fixed at a predetermined value.

Therefore, in a conventional process of assembling semiconductor packageboards, because the standard sizes of the strip format of thesemiconductor package board and the panel are maintained constant, noeffort to increase the number of strip formats of semiconductor packageboards that can be mounted to the panel has been attempted. However, torespond to the trend of decreasing process duration and improvingprocess efficiency in the process of manufacturing the semiconductorpackage board, the limitation of the number of strip formats ofsemiconductor package boards that can be mounted to the panel must beovercome.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made keeping in mind theabove problems occurring in the prior art, and an object of the presentinvention is to provide a strip format of a semiconductor package boardand an array thereof in which a dummy area is formed into apredetermined shape such that, when several strip formats are arrangedon a panel, the number of strip formats arranged on the panel can beincreased compared to the conventional art.

Another object of the present invention is to provide a strip format ofa semiconductor package board and an array thereof in which the couplingrelationship between strip formats is improved, because the dummy areasof the strip formats are formed into the above-mentioned shapes.

In an aspect, the present invention provides a strip format of asemiconductor package board, including: a package area, to which asemiconductor device is mounted, with an outer layer circuit patternformed in the package area; and a dummy area surrounding the packagearea. The dummy area is formed into a predetermined shape to improve acoupling relationship between the strip format and another strip format.

The shape of the dummy area may be defined by prominence and depressionparts having various shapes such that the strip formats engage eachother.

In another aspect, the present invention provides a panel array forarranging strip formats of semiconductor package boards, including: aplurality of strip formats of semiconductor package boards, each of thestrip formats comprising a package area to which a semiconductor deviceis mounted, with an outer layer circuit pattern formed in the packagearea, and a dummy area surrounding the package area and having apredetermined shape; and a panel, on which the plurality of stripformats of the semiconductor package boards are arranged at regularintervals.

The shape of the dummy area of each of the strip formats of thesemiconductor package boards may be defined by prominence and depressionparts having various shapes such that the strip formats engage with eachother.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a perspective view of a conventional strip format of asemiconductor package board;

FIG. 2 is a view showing conventional strip formats of semiconductorpackage boards arrayed on a panel;

FIG. 3 is a view showing a strip format, according to a first embodimentof the present invention;

FIG. 4 is a view showing the strip formats of FIG. 3 connected to eachother;

FIG. 5 is a view showing the strip formats of FIG. 3 arrayed on a panel;

FIG. 6 is a view showing a strip format, according to a secondembodiment of the present invention;

FIG. 7 is a view showing the strip formats of FIG. 6 connected to eachother; and

FIG. 8 is a view showing the strip formats of FIG. 6 arrayed on a panel.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the present invention will be described in detail withreference to the attached drawings.

For reference, FIG. 3 illustrates a strip format of a PBGA (plastic ballgrid array) semiconductor package board, according to a first embodimentof the present invention. FIG. 4 illustrates the strip formats coupledto each other. FIG. 5 illustrates the strip formats of the PBGAsemiconductor package boards which are arrayed on a panel. FIGS. 6through 8 illustrate the case of use of a CSP (chip-size package)semiconductor package board, according to a second embodiment of thepresent invention.

As described above, the present invention provides a method ofincreasing the number of strip formats of semiconductor package boardsto be arrayed on a panel. In detail, the present invention ischaracterized in that the strip format is formed into a predeterminedshape such that unnecessary portions are maximally removed from a dummyarea provided in the area surrounding the strip format of thesemiconductor package board, thus achieving the above-mentioned object.That is, the present invention achieves the above-mentioned object usinga technical characteristic in which the dummy area is removed before apackage area is mounted to a mother board after a semiconductor devicehas been mounted to a semiconductor device mounting part.

The strip format of the PBGA semiconductor package board according tothe first embodiment of the present invention having the above-mentionedtechnical characteristic will be explained in detail herein below. Thestrip format 100 of the semiconductor package board according to thepresent invention is shown in FIG. 3. As shown in the drawing, the stripformat 100 of the semiconductor package board includes a package area110, which has a semiconductor device mounting part 110 a and an outerlayer circuit pattern 110 b, and a dummy area 120, which surrounds thepackage area 110, and on which a copper pattern is formed. The dummyarea 120 has a predetermined shape which includes prominence parts anddepression parts.

Here, the package area 110 is mounted to the mother board or the like ina state in which the dummy area 120 is removed after a semiconductordevice has been mounted to and packaged on the semiconductor devicemounting part 110 a. Furthermore, an inner layer pattern (not shown) aswell as the outer layer circuit pattern 110 b is formed in the packagearea 110, so that the package area 110 transmits and receives electricalsignals to and from the semiconductor device.

The semiconductor device mounting part 110 a is an area for mounting asemiconductor device thereon, and is typically placed on the centralportion of the package area 110. Here, the semiconductor device, whichis mounted to the semiconductor device mounting part 110 a, iselectrically connected to a wire bonding pad or a solder ball pad, whichis provided on the outer layer circuit pattern 110 b. Furthermore, todissipate heat from the semiconductor device, which is mounted to thesemiconductor device mounting part 110 a, it is preferable that thesemiconductor device mounting part 110 a be made of conductive material(for example, copper or gold).

The outer layer circuit pattern 110 b is formed around the semiconductordevice mounting part 110 a. The wire bonding pad or solder ball pad ofthe outer layer circuit pattern 110 b, which is electrically connectedto the semiconductor device mounted to the semiconductor device mountingpart 110 a, is exposed outside a solder resist pattern (not shown).

The dummy area 120 is an area that is removed before the package area110 is mounted to the mother board or the like after the semiconductordevice has been mounted to the semiconductor device mounting part 110 a.The dummy area 120 surrounds the package area 110. The present inventionis technically characterized in that the dummy area 120 is formed into apredetermined shape. In detail, one edge of the strip format 100, thatis, one edge of the dummy area 120, is formed into a shape such thattrapezoidal prominence parts 130 and trapezoidal depression parts 140are alternately arranged. Furthermore, the opposite edge of the stripformat 100 is formed into a shape in which trapezoidal depression parts150 are formed at positions corresponding to the respective trapezoidalprominence parts 130, and trapezoidal prominence parts 160 are formed atpositions corresponding to the respective trapezoidal depression parts140. As such, the strip format 100 of the semiconductor package board ofthe present invention is technically characterized in that the dummyarea 120 is formed into the above-mentioned shape. In the firstembodiment, although the prominence parts and the depression parts ofthe dummy area 120 have been illustrated as having trapezoidal shapes,the present invention is not limited thereto. In other words, theirshapes are not limited to any particular shapes as long as they make itpossible to smoothly couple strip formats to each other.

The arrangement of the strip formats 100 of the semiconductor packageboards having the above-mentioned shapes is shown in FIG. 4. Referringto FIG. 4, two strip formats 100 are arranged such that the prominenceparts and the depression parts of the dummy areas 120 thereof arealigned with each other and smoothly engage with each other. Therefore,the height of the strip formats 100 of the semiconductor package boardsof the present invention having the above-mentioned arrangement is lessthan that of the conventional arranged strip formats of thesemiconductor package boards. Furthermore, the coupling between thestrip formats in the array of the present invention is maintained morestable, compared to the conventional art.

Meanwhile, FIG. 5 shows the strip formats 100 of the semiconductorpackage boards arranged on the panel 200. As shown in FIG. 5, in thepresent invention, twelve strip formats 100 of the semiconductor packageboards are arranged on the panel 200. That is, compared to theconventional art, in which ten strip formats of semiconductor packageboards can be arranged on a panel having the same size as the panel 200of FIG. 5, the number of strip formats 100 of the semiconductor packageboards in the present invention is increased by 20%. As such, it isunderstood that the above-mentioned object of the present invention canachieved by arranging the strip formats 100 of the semiconductor packageboards such that the prominence and depression parts 130, 140, 150 and160 are aligned with each other.

FIG. 6 is a view showing a strip format 300 of a CSP semiconductorpackage board, according to the second embodiment of the presentinvention. As shown in the drawing, the second embodiment of the presentinvention is technically characterized in that rectangular depressionparts 320 and rectangular prominence parts 330 are formed in one edge ofa dummy area 310 of the strip format 300 of the semiconductor packageboard. That is, it is to be understood that a portion of the dummy area300 corresponding to the rectangular depression parts 320 is removedfrom the dummy area 300.

FIG. 7 is a view showing the connection between two strip formats 300 ofthe semiconductor package boards according to the second embodiments.The dummy area 310 of the strip format 300 according to the secondembodiment is formed such that ‘a’ of FIG. 7 is 1.5 mm, ‘b’ is 15, 558mm, and ‘c’ is 8,758 mm. Here, the standard size of the strip format 300is 212×63.424, that is, the overall size thereof is not changed. Assuch, it is appreciated that the above-mentioned object of the presentinvention can be achieved by forming the dummy area 310 of the stripformat 300 of the semiconductor package board into the above shape.

FIG. 8 shows the several strip formats 300 of the semiconductor packageboards according to the second embodiment, which are arranged on a panel200. In FIG. 8, twelve strip formats 300 of the semiconductor packageboards are provided on the panel 200. Here, it is to be appreciated thatthe number of strip formats 300 of the semiconductor package boards isalso increased by 20% compared to the conventional art.

Meanwhile, in the two above-mentioned embodiments of the presentinvention, although it has been illustrated that twelve strip formats ofsemiconductor package boards can be provided on a single panel, thenumber of strip formats of semiconductor package boards is not limitedto this, and the number thereof may be changed depending on the shape ofthe dummy area.

As described above, in a strip format of a semiconductor package boardaccording to the present invention, a dummy area is formed into apredetermined shape such that, when several strip formats are arrangedon a panel, the number of strip formats arranged on the panel can beincreased compared to that of the conventional art, thus enhancing theefficiency of a process of assembling the semiconductor package boards.

Furthermore, the present invention is advantageous in that the couplingrelationship between the strip formats is improved because the dummyarea of the strip format is formed into the shape disclosed in thepresent invention. Thereby, there is an advantage in that the error in amanufacturing process is markedly reduced.

Although the preferred embodiments of the present invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

1. A strip format of a semiconductor package board, comprising: apackage area, to which a semiconductor device is mounted, with an outerlayer circuit pattern formed in the package area; and a dummy areasurrounding the package area, wherein the dummy area is formed into apredetermined shape to improve a coupling relationship between the stripformat and another strip format.
 2. The strip format of thesemiconductor package board as set forth in claim 1, wherein the shapeof the dummy area is defined by prominence and depression parts havingvarious shapes such that the strip formats engage each other.
 3. A panelarray for arranging strip formats of semiconductor package boards,comprising: a plurality of strip formats of semiconductor packageboards, each of the strip formats comprising a package area to which asemiconductor device is mounted, with an outer layer circuit patternformed in the package area, and a dummy area surrounding the packagearea and having a predetermined shape; and a panel, on which theplurality of strip formats of the semiconductor package boards arearranged at regular intervals.
 4. The panel array as set forth in claim3, wherein the shape of the dummy area of each of the strip formats ofthe semiconductor package boards is defined by prominence and depressionparts having various shapes such that the strip formats engage with eachother.